The present application relates to solid-state image intensifiers, specifically to an image intensifier fabricated in a monolithic form on a single piece of a semiconductor substrate using standard semiconductor Integrated Circuit (IC) manufacturing methods. In particular, the invention relates to solid-state image sensor/intensifiers which exploit charge multiplication by single carrier impact ionization.
An Image Intensifier (or "II") is an image-sensing device that has the ability to convert an image, formed by only a few or a single photon per pixel, to many electrons per pixel without adding any appreciable noise. This is advantageous in many low-light-level imaging applications, since the image signal formed by many electrons per pixel is easier to detect and process. The signal, consisting of many electrons instead of only one, can always be kept above the charge detector and system noise floor.
Traditionally, image-intensifying detectors have used vacuum tube devices. In such devices an image is projected onto a suitable photo-cathode, and the liberated photoelectrons are multiplied on their way to the anode. The multiplication method typically used is based on a micro-channel concept where electrons are multiplied several hundred or a thousand times before they are sensed. The resulting multiplied image charge is then either scanned or directly displayed on a suitable anode viewing screen. Such devices are used today in military night vision scopes and other low-light-level image sensing cameras. While these devices achieve a superb performance and have many desirable characteristics such as low power consumption and a very high sensitivity, they also have undesirable characteristics that are not easily overcome. The vacuum tube technology does not lend itself to low cost-high volume production, significant miniaturization, color sensing, and an easy interface with today's modern digital image processing systems. The vacuum tube intensifiers also require high voltages for their operation. For these and other reasons described herein, the current research efforts have focussed on developing image intensifier devices that can be fabricated using standard semiconductor manufacturing technology.
An example of such work, using a hybrid approach, is found in T. Watabe et al., "CMOS Image Sensor Overlaid with HARP Photoconversion Layer", PROCEEDINGS OF 1999 IEEE WORKSHOP ON CHARGE-COUPLED DEVICES AND ADVANCED IMAGE SENSORS (Jun. 10-12, 1999, Karuizawa, Nagano, Japan), paper R33, which is hereby incorporated by reference.
Another example of the image intensifier concept, implemented monolithically and directly in a solid state semiconductor substrate, is described in U.S. Pat. No. 5,337,340 to Hynecek (1994), which is also hereby incorporated by reference.
U.S. Pat. No. 4,912,536 to Lou describes yet another non-imaging device that represents an accumulation and multiplication photodetector having three adjacent MOS gates formed on a suitable substrate. The first gate is biased such that a depletion well is formed underneath that accumulates photocharge. The second gate is a transfer gate that isolates the accumulation well from the avalanche well formed under the third, avalanche, gate. After the third gate is biased into the avalanche-ready condition, the second gate is opened and accumulated charge from the accumulation well is transferred into the avalanche well. During the charge transfer process charge undergoes amplification by a multiplication factor associated with the avalanche process.
Known monolithic image sensors, such as CCD or CMOS based devices, have achieved high performance in resolution, sensitivity, noise, and miniaturization. Camcorders and popular Digital Still Cameras (DSC), that employ these sensors and are successfully competing with film, would not be possible without them. However, the reduction in chip size needed for cost competitiveness requires a reduction in pixel size. Unfortunately, as the pixel size is reduced, there is an associated and unavoidable reduction in sensitivity that leads to a reduction in S/N ratio. The reduction in S/N ratio is due to the fixed charge detector noise floor that is not easily reduced. It seems difficult to reduce the noise floor of the on-chip charge detectors to a single electron or below. Therefore, the charge multiplication concept, as described in U.S. Pat. No. 5,337,340, holds out the promise of achieving a competitive performance advantage within the image intensifier technologies since charge multiplication can improve sensitivity without an appreciable increase in noise.
U.S. Pat. No. 5,337,340 teaches the basic concept of carrier multiplication in a semiconductor and its application to CCD image-sensing devices. When a photon is received in a pixel and converted into an electron, the resulting electron can be transferred in a CCD fashion through a high field region to cause impact ionization. Impact ionization generates a new electron-hole pair and thus increases the original number of electrons. Typically no more than one new electron-hole pair is created per electron transfer, and avalanche multiplication is never allowed to begin. This is one of the features that distinguishes the concept described in U.S. Pat. No. 5,337,340 from the concept described in U.S. Pat. No. 4,912,536. It can be shown theoretically that the impact ionization process is relatively noise free, so the photon generated charge signal can be increased above the system noise floor without reducing the Signal to Noise ratio (S/N). By contrast, avalanching is a noisy process (in which impact ionization generates secondary carriers which themselves generate further secondary carriers).
While the general concept described in the U.S. Pat. No. 5,337,340 is sound, some more recent experimentation has provided some new data on the noise floor of this approach. See Hynecek, "CCM-A New Low-Noise Charge Carrier Multiplier Suitable for Detection of Charge in Small Pixel CCD Image Sensors", 39 IEEE TRANSACTIONS ON ELECTRON DEVICES 1972 (1992). A Single Photon Detection (SPD) by monolithic Solid State Image Sensors thus remains a desirable goal.
FIGS. 1 and 2 show a plan view and a cross section of a CCD unit cell 101 used in typical CCD image sensors before the final dielectric layer overcoat and the metal patterning steps have been applied to the structure. In FIG. 1, channel stop regions 104 and 106 confine charge in the Y direction while gate electrodes 102 and 103 together with the Virtual Electrode (VE) region 105 confine charge in the X direction. The CCD channel is defined between the channel stops 104 and 106. The electrical interconnect lines that apply clock signals f1 and f2 to the physical structures are shown symbolically. By applying suitable biases to gate electrodes 102 and 103, charge can be transferred up or down the CCD channel. The potential profile for various gate biases in regions 107 and 108 and the resulting charge transfer process is shown in FIG. 2. Potentials in regions 107 and 108 change from level 150 to 152 while the potential of the VE region 105 stays constant at fixed level 151. For completeness, the cross section of the device in the Y direction is shown in FIG. 3 with detail 115 of the channel stop region given in FIG. 4. Regions and structures 102, through 112, 116, 117, and 118 in FIGS. 1 and 2 correspond directly to regions and structures 202, through 212, 216, 217, and 218 in FIGS. 5 and 6 that will be discussed in more detail later.
Background charge generation is best understood with reference to FIG. 4. When a bias applied to gate electrode 103 is low, holes 119 are trapped at the interface between semiconductor substrate 112 and gate dielectric 118. As the bias applied to gate electrode 103 is changed from low to high level, holes 119 that have been trapped at the interface are suddenly released and accelerated. The trapped holes have been uncovered due to the change in the depletion region boundary from location 113 to 114. As the accelerated holes gain energy they cause impact ionization and generation of electrons 120. Since almost all CCD devices have the topology shown in FIG. 1, where gate electrodes 102 and 103 overlap the channel stops 104 and 106, the generation of unwanted charge cannot be easily avoided. This is true for the structure shown in FIG. 1, representing only an example here, as well as for other more common CCD devices that have more than two gate electrodes and no VE regions 105. Devices that have VE regions and either multiple gate electrodes or a single gate electrode have an additional problem of background charge generation at the interfaces between the regions 102 and 105 and the regions 103 and 105.
In modern CCD devices, holes are usually attracted to the substrate-dielectric interface intentionally to lower the dark current generated during the image integration period. Since the hole trapping at the interface causes the background charge generation and corresponding noise it is difficult to see how to achieve an image intensifier operation according to prior art. It is also difficult to achieve an image intensifier operation without the background charge generation in the CCD devices that are very small and that are built using conventional layout techniques.
The prior art does not disclose a gate electrode structure in which is formed an aperture over which a charge multiplication electrode is disposed. The prior art does not disclose a method in which initially detected charge in storage well is multiplied by single-carrier impact ionization process instead of an avalanche process. The prior art does not disclose a method in which a significant multiplication gain, without background noise generation, is achieved using a repetitive charge transfer back and forth within a single cell or by using many cells connected together in a CCD fashion. The prior art does not disclose a method of achieving an externally programmable charge gain by controlling the number of multiplication transfers within one cell.
A Semiconductor Image Intensifier
The present inventor has discovered that the noise floor of the device described in Hynecek U.S. Pat. No. 5,337,340 can be improved by minimizing the coupling of the high electric fields in the carrier-multiplication area to the channel stop. The present application therefore discloses a variety of structures in which this coupling is reduced, and noise performance is therefore improved. In many embodiments the region of high electric field lies within the cell area, which is laterally delimited by the channel stops and transfer barriers, but does not overlie the channel stops anywhere. Preferably the high-field region lies entirely within a depleted semiconductor volume.
The present application discloses an improved solid-state carrier multiplication stage, and imaging chips incorporating this stage, which provide improved immunity to dark current noise. In various embodiments, the application discloses a practical charge multiplication pixel that can be operated without generation of background charge. These and other objects are achieved in a cell of sensors that includes a channel formed in a substrate, a gate structure insulatively disposed over and transverse to the channel having an aperture formed therein, and a charge multiplication gate electrode insulatively disposed over the aperture. In one embodiment, the gate electrode structure includes a first aperture gate electrode having the aperture formed therethrough. In another embodiment, the gate electrode structure includes first and second aperture gate electrodes having respective first and second reticulations therein so as to frame the aperture. Additional embodiments include three or more gate electrodes through which is formed the aperture.
In an alternative embodiment, a method of multiplying charge collected in a storage well includes forming a multiplication well under a charge multiplication gate and a potential barrier under the charge transfer gate, the potential barrier being lowered until initial charge stored in the storage well transfers over the barrier into the multiplication well. Transferred charge causes single carrier impact ionization resulting in multiplying originally transferred charge. The method further includes transferring multiplied charge from the multiplication well back into the storage well or transferring it into a storage well of an adjacent cell connected to it in a CCD fashion.
The disclosed innovations, in various embodiments, provide one or more of at least the following advantages:
the charge gain of photocells or photo-detector pixels of image sensors can be programmed or controlled by electronic signals applied externally to the chip. (This is because it is possible to control the charge multiplication by altering the voltage on the multiplication gate electrodes, or by controlling the number of pulses used in multiplication cycles.) PA1 a practical high performance monolithic Solid State Image Intensifier (SSII) in any of various architectures.